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x86: Add missing reg_opcode constraint to lockable INC #6566

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The INC encoding is FE /0 meaning that a reg_opcode=0 constraint is needed in SLEIGH. This is missing from the memory variant (in lockable.sinc), which causes undefined FE xx instructions to be decoded as INC.

(Without this constraint, the constructors technically overlap with the DEC instruction, however, since the DEC instruction has the correct constraints it ends up getting matched first).

e.g.,

  • fe3f
    • Hardware Reference (AMD CPU & Intel CPU): #UD (Invalid Opcode Exception)
    • x86:LE:64:default (Existing): "INC byte ptr [RDI]"
    • x86:LE:64:default (This patch): (Invalid)

@GhidorahRex GhidorahRex self-assigned this May 23, 2024
@GhidorahRex GhidorahRex added Type: Bug Something isn't working Feature: Processor/x86 Status: Triage Information is being gathered labels May 23, 2024
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Feature: Processor/x86 Status: Triage Information is being gathered Type: Bug Something isn't working
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